1. Field of the Invention
The present invention relates to a power semiconductor device used for controlling high power, and particularly to a field effect transistor (MOS FET (Metal-Oxide-Semiconductor Field-Effect Transistor)) of the vertical type.
2. Description of the Related Art
The on-resistance of a vertical type power MOS FET greatly depends on the electric resistance of a conducting layer portion (drift layer). The doping concentration that determines the electric resistance of the drift layer cannot exceed a certain limit in relation to the breakdown voltage of a pn junction formed between the base layer and drift layer. Accordingly, there is a tradeoff relationship between the device breakdown voltage and on-resistance. Overcoming this tradeoff is important in the realization of a device of low power consumption. In relation to this tradeoff, there is a limit determined by the device material, which needs to be exceeded to realize a power MOS FET with an on-resistance lower than conventional devices.
As an example of a vertical type power MOS FET that solves the problems described above, there is a structure, known as a “superjunction structure”, in which a p-pillar layer and an n-pillar layer are buried at a position corresponding to a drift layer. In the superjunction structure, the p-pillar layer and n-pillar layer are set to contain the same charge amount (impurity amount), so that a pseudo non-doped layer is created to hold a high breakdown voltage. Further, the n-pillar layer doped at a high concentration is used for electric current to flow therethrough, thereby realizing a low on-resistance beyond the present material limits. Furthermore, where an n−-layer is disposed below the superjunction structure, the tradeoff between the breakdown voltage and on-resistance is improved, as compared with the case of the superjunction structure alone.
A brief explanation will be given of the following Patent publications 1 to 5 listed as related art in relation to the superjunction structure.
[Patent publication 1] Jpn. Pat. Appln. KOKAI Publication No. 2003-101022
[Patent publication 2] Jpn. Pat. Appln. KOKAI Publication No. 2004-119611
[Patent publication 3] Jpn. Pat. Appln. KOKAI Publication No. 2004-72068
[Patent publication 4] Jpn. Pat. Appln. KOKAI Publication No. 2004-214511
[Patent publication 5] U.S. Pat. No. 6,693,338
Patent publication 1 discloses a power MOS FET including a vertical type superjunction structure formed of an n-layer and a p-RESURF layer. In this device, an n−-drift layer having a lower impurity concentration than the n-layer is disposed on the drain side. When a high voltage is applied, the n-layer and p-RESURF layers are completely depleted.
Patent publication 2 discloses a power MOS FET including a vertical type superjunction structure formed of an n−-drift layer and a p-RESURF layer. In this device, the p-RESURF layer has an impurity concentration distributed such that the concentration decreases with increase in the depth (inclination profile). This arrangement prevents the breakdown voltage from decreasing due to imbalance between impurity amounts of the p-RESURF layer and n−-drift layer.
Patent publication 3 discloses a power MOS FET including a vertical type superjunction structure formed of an n-drift region and a p-partition region. In this device, the p-partition region has a higher impurity concentration than the n-drift region on the substrate top side, and vice versa on the substrate bottom side. This arrangement improves the avalanche withstanding capability.
Patent publication 4 discloses a power MOS FET including a vertical type superjunction structure formed of an n-pillar layer and a p-pillar layer. In this device, an n−-drift layer having a lower impurity concentration than the n-pillar layer is disposed on the drain side. The ratio (t/t+d) of the thickness t of the n−-drift layer relative to the total thickness t+d of the n−-drift layer and superjunction structure is set to be 0.72 or less.
Patent publication 5 discloses a power MOS FET including a vertical type superjunction structure formed of an n-second drift layer and a p-RESURF layer. In one type of the devices disclosed in this publication, an n--drift layer having a lower impurity concentration than the n-layer is disposed on the drain side. In another type of the devices disclosed in this publication, no n31 -drift layer is disposed, and the interior structure or depth of the p-RESURF layer is variously changed.